MC9S12HZ256 Datasheet, PDF (115/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 4
Port Integration Module (PIM9HZ256V2)
4.1 lntroduction
The port integration module establishes the interface between the peripheral modules and the I/O pins for
for ports AD, L, M, P, T, U and V.
This section covers:
• Port A, B, E, and K and the BKGD pin, which are shared between the core logic (including
multiplexed bus interface) and the LCD driver
• Port AD associated with ATD module (channels 7 through 0) and keyboard wake-up interrupts
• Port L connected to the LCD driver and ATD (channels 15 through 8) modules
• Port M connected to 2 CAN modules
• Port P connected to 1 SCI, 1 IIC and PWM modules
• Port S connected to 1 SCI and 1 SPI modules
• Port T connected to the timer module (TIM) and the LCD driver
• Port U and V associated with PWM motor control and stepper stall detect modules
Each I/O pin can be configured by several registers: input/output selection, drive strength reduction,
enable and select of pull resistors, wired-or mode selection, interrupt enable, and/or status flags.
NOTE
Ports A, B, E and K, and the BKGD pin are shared between core logic
(including multiplexed bus interface) and the LCD driver. Refer to the
MEBI block description chapter for details on these ports.
4.1.1 Features
A standard port has the following minimum features:
• Input/output selection
• 5-V output drive with two selectable drive strength (or slew rates)
• 5-V digital and analog input
• Input with selectable pull-up or pull-down device
Optional features:
• Open drain for wired-OR connections
• Interrupt input with glitch filtering
MC9S12HZ256 Data Sheet, Rev. 2.04
Freescale Semiconductor
115