MC9S12HZ256 Datasheet, PDF (135/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

4.3.3.3
Chapter 4 Port Integration Module (PIM9HZ256V2)
Port M Data Direction Register (DDRM)
7
6
5
4
3
2
1
0
R
0
0
0
0
DDRM5
DDRM4
DDRM3
DDRM2
W
Reset
0
0
0
0
0
0
0
0
= Reserved or Unimplemented
Figure 4-18. Port M Data Direction Register (DDRM)
Read: Anytime. Write: Anytime.
This register configures port pins PM[5:2] as either input or output.
When a CAN module is enabled, the corresponding transmitter (TXCANx) pin becomes an output, the
corresponding receiver (RXCANx) pin becomes an input, and the associated Data Direction Register bits
have no effect. If a CAN module is disabled, the corresponding Data Direction Register bit reverts to
control the I/O direction of the associated pin.
Table 4-13. DDRM Field Descriptions
Field
5:2
Data Direction Port M
DDRM[5:2] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
Description
4.3.3.4 Port M Reduced Drive Register (RDRM)
7
6
5
4
3
2
1
0
R
0
0
0
0
RDRM5
RDRM4
RDRM3
RDRM2
W
Reset
0
0
0
0
0
0
0
0
= Reserved or Unimplemented
Figure 4-19. Port M Reduced Drive Register (RDRM)
Read: Anytime. Write: Anytime.
This register configures the drive strength of configured output pins as either full or reduced. If a pin is
configured as input, the corresponding Reduced Drive Register bit has no effect.
Table 4-14. RDRM Field Descriptions
Field
Description
5:2
Reduced Drive Port M
RDRM[5:2] 0 Full drive strength at output
1 Associated pin drives at about 1/3 of the full drive strength.
MC9S12HZ256 Data Sheet, Rev. 2.04
Freescale Semiconductor
135