MC9S12HZ256 Datasheet, PDF (361/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 12 Freescale’s Scalable Controller Area Network (MSCANV2)
Write: For transmit buffers, anytime when TXEx flag is set (see Section 12.3.2.7, “MSCAN Transmitter
Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
Section 12.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). Unimplemented for
receive buffers.
Reset: Undefined (0x00XX) because of RAM-based implementation
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
R
IDR0
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
W
R
IDR1
ID2
ID1
ID0
RTR
IDE (=0)
W
R
IDR2
W
R
IDR3
W
= Unused, always read ‘x’
Figure 12-22. Receive/Transmit Message Buffer — Standard Identifier Mapping
12.3.3.1 Identifier Registers (IDR0–IDR3)
The identifier registers for an extended format identifier consist of a total of 32 bits; ID[28:0], SRR, IDE,
and RTR bits. The identifier registers for a standard format identifier consist of a total of 13 bits; ID[10:0],
RTR, and IDE bits.
12.3.3.1.1 IDR0–IDR3 for Extended Identifier Mapping
R
W
Reset:
7
ID28
6
ID27
5
ID26
4
ID25
3
ID24
2
ID23
1
ID22
x
x
x
x
x
x
x
Figure 12-23. Identifier Register 0 (IDR0) — Extended Identifier Mapping
0
ID21
x
Table 12-26. IDR0 Register Field Descriptions — Extended
Field
7:0
ID[28:21]
Description
Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the
most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an
identifier is defined to be highest for the smallest binary number.
MC9S12HZ256 Data Sheet, Rev. 2.04
Freescale Semiconductor
361