MC9S12HZ256 Datasheet, PDF (397/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 13 Serial Communication Interface (SCIV4)
Table 13-7. SCISR1 Field Descriptions (continued)
Field
Description
3
Overrun Flag² — OR is set when software fails to read the SCI data register before the receive shift register
OR
receives the next frame. The OR bit is set immediately after the stop bit has been completely received for the
second frame. The data in the shift register is lost, but the data already in the SCI data registers is not affected.
Clear OR by reading SCI status register 1 (SCISR1) with OR set and then reading SCI data register low
(SCIDRL).
0 No overrun
1 Overrun
2
Noise Flag — NF is set when the SCI detects noise on the receiver input. NF bit is set during the same cycle as
NF
the RDRF flag but does not get set in the case of an overrun. Clear NF by reading SCI status register 1(SCISR1),
and then reading SCI data register low (SCIDRL).
0 No noise
1 Noise
1
Framing Error Flag — FE is set when a logic 0 is accepted as the stop bit. FE bit is set during the same cycle
FE
as the RDRF flag but does not get set in the case of an overrun. FE inhibits further data reception until it is
cleared. Clear FE by reading SCI status register 1 (SCISR1) with FE set and then reading the SCI data register
low (SCIDRL).
0 No framing error
1 Framing error
0
Parity Error Flag — PF is set when the parity enable bit (PE) is set and the parity of the received data does not
PF
match the parity type bit (PT). PF bit is set during the same cycle as the RDRF flag but does not get set in the
case of an overrun. Clear PF by reading SCI status register 1 (SCISR1), and then reading SCI data register low
(SCIDRL).
0 No parity error
1 Parity error
1 _{When the receiver wakeup bit (RWU) is set, an idle line condition does not set the IDLE flag.}
2 _{The OR flag may read back as set when RDRF flag is clear. This may happen if the following sequence of events occurs:}
1. After the first frame is received, read status register SCISR1 (returns RDRF set and OR flag clear);
2. Receive second frame without reading the first frame in the data register (the second frame is not received and OR flag
is set);
3. Read data register SCIDRL (returns first frame and clears RDRF flag in the status register);
4. Read status register SCISR1 (returns RDRF clear and OR set).
Event 3 may be at exactly the same time as event 2 or any time after. When this happens, a dummy SCIDRL read following
event 4 will be required to clear the OR flag if further frames are to be received.
MC9S12HZ256 Data Sheet, Rev. 2.04
Freescale Semiconductor
397