MC9S12HZ256 Datasheet, PDF (458/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
7
6
5
4
3
2
1
0
R Bit 7
6
5
4
3
2
1
Bit 0
W
0
0
0
0
0
0
0
0
Reset
0
0
0
0
0
0
0
0
Figure 15-18. PWM Channel Counter Registers (PWMCNT3)
7
6
5
4
3
2
1
0
R Bit 7
6
5
4
3
2
1
Bit 0
W
0
0
0
0
0
0
0
0
Reset
0
0
0
0
0
0
0
0
Figure 15-19. PWM Channel Counter Registers (PWMCNT4)
7
6
5
4
3
2
1
0
R Bit 7
6
5
4
3
2
1
Bit 0
W
0
0
0
0
0
0
0
0
Reset
0
0
0
0
0
0
0
0
Figure 15-20. PWM Channel Counter Registers (PWMCNT5)
Read: anytime
Write: anytime (any value written causes PWM counter to be reset to 0x0000).
15.3.2.13 PWM Channel Period Registers (PWMPERx)
There is a dedicated period register for each channel. The value in this register determines the period of
the associated PWM channel.
The period registers for each channel are double buffered so that if they change while the channel is
enabled, the change will NOT take effect until one of the following occurs:
• The effective period ends
• The counter is written (counter resets to 0x0000)
• The channel is disabled
In this way, the output of the PWM will always be either the old waveform or the new waveform, not some
variation in between. If the channel is not enabled, then writes to the period register will go directly to the
latches as well as the buffer.
NOTE
Reads of this register return the most recent value written. Reads do not
necessarily return the value of the currently active period due to the double
buffering scheme.
Reference Section 15.4.2.3, “PWM Period and Duty,” for more information.
MC9S12HZ256 Data Sheet, Rev. 2.04
458
Freescale Semiconductor