MC9S12HZ256 Datasheet, PDF (542/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 19 Debug Module (DBGV1)
19.3.2.1
Debug Control Register 1 (DBGC1)
NOTE
All bits are used in DBG mode only.
R
W
Reset
7
DBGEN
0
6
5
4
3
2
0
ARM
TRGSEL
BEGIN
DBGBRK
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-4. Debug Control Register (DBGC1)
1
0
CAPMOD
0
0
NOTE
This register cannot be written if BKP mode is enabled (BKABEN in
DBGC2 is set).
Table 19-3. DBGC1 Field Descriptions
Field
Description
7
DBGEN
6
ARM
5
TRGSEL
4
BEGIN
DBG Mode Enable Bit — The DBGEN bit enables the DBG module for use in DBG mode. This bit cannot be
set if the MCU is in secure mode.
0 DBG mode disabled
1 DBG mode enabled
Arm Bit — The ARM bit controls whether the debugger is comparing and storing data in the trace buffer. See
Section 19.4.2.4, “Arming the DBG Module,” for more information.
0 Debugger unarmed
1 Debugger armed
Note: This bit cannot be set if the DBGEN bit is not also being set at the same time. For example, a write of 01
to DBGEN[7:6] will be interpreted as a write of 00.
Trigger Selection Bit — The TRGSEL bit controls the triggering condition for comparators A and B in DBG
mode. It serves essentially the same function as the TAGAB bit in the DBGC2 register does in BKP mode. See
Section 19.4.2.1.2, “Trigger Selection,” for more information. TRGSEL may also determine the type of breakpoint
based on comparator A and B if enabled in DBG mode (DBGBRK = 1). Please refer to Section 19.4.3.1,
“Breakpoint Based on Comparator A and B.”
0 Trigger on any compare address match
1 Trigger before opcode at compare address gets executed (tagged-type)
Begin/End Trigger Bit — The BEGIN bit controls whether the trigger begins or ends storing of data in the trace
buffer. See Section 19.4.2.8.1, “Storing with Begin-Trigger,” and Section 19.4.2.8.2, “Storing with End-Trigger,”
for more details.
0 Trigger at end of stored data
1 Trigger before storing data
MC9S12HZ256 Data Sheet, Rev. 2.04
542
Freescale Semiconductor