MC9S12HZ256 Datasheet, PDF (126/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.1.2 Port AD Input Register (PTIAD)
7
R PTIAD7
W
6
PTIAD6
5
PTIAD5
4
PTIAD4
3
PTIAD3
2
PTIAD2
1
PTIAD1
0
PTIAD0
Reset
1
1
1
1
1
1
1
1
= Reserved or Unimplemented
Figure 4-3. Port AD Input Register (PTIAD)
Read: Anytime. Write: Never; writes to these registers have no effect.
If the ATDDIEN1 bit of the associated I/O pin is set to 0 (digital input buffer is disabled), a read returns a
1. If the ATDDIEN1 bit of the associated I/O pin is set to 1 (digital input buffer is enabled), a read returns
the status of the associated pin.
4.3.1.3 Port AD Data Direction Register (DDRAD)
7
R
DDRAD7
W
Reset
0
6
DDRAD6
5
DDRAD5
4
DDRAD4
3
DDRAD3
2
DDRAD2
0
0
0
0
0
Figure 4-4. Port AD Data Direction Register (DDRAD)
1
DDRAD1
0
0
DDRAD0
0
Read: Anytime. Write: Anytime.
This register configures port pins PAD[7:0] as either input or output.
If a data direction bit is 0 (pin configured as input), then a read value on PTADx depends on the associated
ATDDIEN1 bit. If the associated ATDDIEN1 bit is set to 1 (digital input buffer is enabled), a read on
PTADx returns the value on port AD pin. If the associated ATDDIEN1 bit is set to 0 (digital input buffer
is disabled), a read on PTADx returns a 1.
Table 4-3. DDRAD Field Descriptions
Field
7:0
Data Direction Port AD
DDRAD[7:0] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
Description
MC9S12HZ256 Data Sheet, Rev. 2.04
126
Freescale Semiconductor