MC9S12HZ256 Datasheet, PDF (268/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 9 Motor Controller (MC10B8CV1)
9.3.2.4 Motor Controller Channel Control Registers
Each PWM channel has one associated control register to control output delay, PWM alignment, and
output mode. The registers are named MCCC0... MCCC7. In the following, MCCC0 is described as a
reference for all eight registers.
7
6
5
4
3
2
1
0
R
0
MCOM1
MCOM0
MCAM1
MCAM0
W
0
CD1
CD0
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-7. Motor Controller Control Register Channel 0–7 (MCCC0–MCCC7)
Table 9-5. MCCC0–MCCC7 Field Descriptions
Field
Description
7:6
Output Mode — MCOM1, MCOM0 control the PWM channel’s output mode. See Table 9-6.
MCOM[1:0]
5:4
MCAM[1:0]
PWM Channel Alignment Mode — MCAM1, MCAM0 control the PWM channel’s PWM alignment mode and
operation. See Table 9-7.
MCAM[1:0] and MCOM[1:0] are double buffered. The values used for the generation of the output waveform
will be copied to the working registers either at once (if all PWM channels are disabled or MCPER is set to 0)
or if a timer counter overflow occurs. Reads of the register return the most recent written value, which are not
necessarily the currently active values.
1:0
PWM Channel Delay — Each PWM channel can be individually delayed by a programmable number of PWM
CD[1:0]
timer counter clocks. The delay will be n/f_TC. See Table 9-8.
MCOM[1:0]
00
01
10
11
MCAM[1:0]
00
01
10
11
Table 9-6. Output Mode
Output Mode
Half H-bridge mode, PWM on MnCxM, MnCxP is released
Half H-bridge mode, PWM on MnCxP, MnCxM is released
Full H-bridge mode
Dual full H-bridge mode
Table 9-7. PWM Alignment Mode
PWM Alignment Mode
Channel disabled
Left aligned
Right aligned
Center aligned
MC9S12HZ256 Data Sheet, Rev. 2.04
268
Freescale Semiconductor