MC9S12HZ256 Datasheet, PDF (125/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.1 Port AD
Port AD is associated with the analog-to-digital converter (ATD) and keyboard wake-up (KWU)
interrupts. Each pin is assigned to these modules according to the following priority: ATD > KWU >
general-purpose I/O.
For the pins of port AD to be used as inputs, the corresponding bits of the ATDDIEN1 register in the ATD
module must be set to 1 (digital input buffer is enabled). The ATDDIEN1 register does not affect the port
AD pins when they are configured as outputs.
Refer to the ATD block description chapter for information on the ATDDIEN1 register.
During reset, port AD pins are configured as high-impedance analog inputs (digital input buffer is
disabled).
4.3.1.1 Port AD I/O Register (PTAD)
R
W
KWU:
ATD:
Reset
7
PTAD7
KWAD7
AN7
0
6
PTAD6
5
PTAD5
4
PTAD4
3
PTAD3
2
PTAD2
KWAD6
AN6
0
KWAD5
KWAD4
KWAD3
KWAD2
AN55
AN4
AN3
AN2
0
0
0
0
Figure 4-2. Port AD I/O Register (PTAD)
1
PTAD1
KWAD1
AN1
0
0
PTAD0
KWAD0
AN0
0
Read: Anytime. Write: Anytime.
If the data direction bit of the associated I/O pin (DDRADx) is set to 1 (output), a write to the
corresponding I/O Register bit sets the value to be driven to the Port AD pin. If the data direction bit of the
associated I/O pin (DDRADx) is set to 0 (input), a write to the corresponding I/O Register bit takes place
but has no effect on the Port AD pin.
If the associated data direction bit (DDRADx) is set to 1 (output), a read returns the value of the I/O register
bit.
If the associated data direction bit (DDRADx) is set to 0 (input) and the associated ATDDIEN1 bits is set
to 0 (digital input buffer is disabled), the associated I/O register bit (PTADx) reads “1”.
If the associated data direction bit (DDRADx) is set to 0 (input) and the associated ATDDIEN1 bits is set
to 1 (digital input buffer is enabled), a read returns the value of the pin.
MC9S12HZ256 Data Sheet, Rev. 2.04
Freescale Semiconductor
125