MC9S12HZ256 Datasheet, PDF (494/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 16 Timer Module (TIM16B8CV1)
16.3.2.16 Pulse Accumulator Flag Register (PAFLG)
7
6
5
4
3
2
1
R
0
0
0
0
0
0
PAOVF
W
Reset
0
0
0
0
0
0
0
Unimplemented or Reserved
Figure 16-25. Pulse Accumulator Flag Register (PAFLG)
0
PAIF
0
Read: Anytime
Write: Anytime
When the TFFCA bit in the TSCR register is set, any access to the PACNT register will clear all the flags
in the PAFLG register.
Table 16-20. PAFLG Field Descriptions
Field
1
PAOVF
0
PAIF
Description
Pulse Accumulator Overflow Flag — Set when the 16-bit pulse accumulator overflows from 0xFFFF to 0x0000.
This bit is cleared automatically by a write to the PAFLG register with bit 1 set.
Pulse Accumulator Input edge Flag — Set when the selected edge is detected at the IOC7 input pin.In event
mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at
the IOC7 input pin triggers PAIF.
This bit is cleared by a write to the PAFLG register with bit 0 set.
Any access to the PACNT register will clear all the flags in this register when TFFCA bit in register TSCR(0x0006)
is set.
MC9S12HZ256 Data Sheet, Rev. 2.04
494
Freescale Semiconductor