MC9S12HZ256 Datasheet, PDF (651/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Appendix A Electrical Characteristics
Table A-20. SPI Slave Mode Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs
Num C
Rating
Symbol
Min
Typ
1 P Operating Frequency
1 P SCK Period t_sck = 1./f_op
2 D Enable Lead Time
3 D Enable Lag Time
4 D Clock (SCK) High or Low Time
5 D Data Setup Time (Inputs)
6 D Data Hold Time (Inputs)
7 D Slave Access Time
8 D Slave MISO Disable Time
9 D Data Valid (after SCK Edge)
10 D Data Hold Time (Outputs)
11 D Rise Time Inputs and Outputs
12 D Fall Time Inputs and Outputs
f_op
t_sck
t_lead
t_lag
t_wsck
t_su
t_hi
t_a
t_dis
t_v
t_ho
t_r
t_f
DC
4
1
1
t_cyc − 30
25
25
0
Max
1/4
2048
1
1
25
25
25
Unit
f_bus
t_bus
t_cyc
t_cyc
ns
ns
ns
t_cyc
t_cyc
ns
ns
ns
ns
A.8
LCD_32F4B
Table A-21. LCD_32F4B Driver Electrical Characteristics
Characteristic
Symbol
Min. Typ.
Max.
Unit
LCD Supply Voltage
VLCD
-0.25
-
VDDX + 0.25
V
LCD Output Impedance(BP[3:0],FP[31:0])
for outputs to charge to higher voltage level or to
GND ¹
Z_BP/FP
-
-
5.0
kΩ
LCD Output Current (BP[3:0],FP[31:0])
for outputs to discharge to lower voltage level
except GND ²
I_BP/FP
50
-
-
uA
1 _{Outputs measured one at a time, low impedance voltage source connected to the VLCD pin.}
2 _{Outputs measured one at a time, low impedance voltage source connected to the VLCD pin.}
A.9 External Bus Timing
A timing diagram of the external multiplexed-bus is illustrated in Figure A-10 with the actual timing
values shown on table Table A-22. All major bus signals are included in the diagram. While both a data
write and data read cycle are shown, only one or the other would occur on a particular bus cycle.
The expanded bus timings are highly dependent on the load conditions. The timing parameters shown
assume a balanced load across all outputs.
MC9S12HZ256 Data Sheet, Rev. 2.04
Freescale Semiconductor
651