MC9S12HZ256 Datasheet, PDF (398/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 13 Serial Communication Interface (SCIV4)
13.3.2.5 SCI Status Register 2 (SCISR2)
7
6
5
4
3
2
1
0
R
0
0
0
RAF
TXPOL
RXPOL
BRK13
TXDIR
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 13-8. SCI Status Register 2 (SCISR2)
Read: anytime
Write: anytime
Table 13-8. SCISR2 Field Descriptions
Field
4
TXPOL
3
RXPOL
2
BRK13
1
TXDIR
0
RAF
Description
Transmit Polarity — This bit control the polarity of the transmitted data. In NRZ format, a 1 is represented by a
mark and a 0 is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA format,
a 0 is represented by short high pulse in the middle of a bit time remaining idle low for a 1 for normal polarity, and
a 0 is represented by short low pulse in the middle of a bit time remaining idle high for a 1 for inverted polarity.
0 Normal polarity
1 Inverted polarity
Receive Polarity — This bit control the polarity of the received data. In NRZ format, a 1 is represented by a mark
and a 0 is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA format, a 0
is represented by short high pulse in the middle of a bit time remaining idle low for a 1 for normal polarity, and a
0 is represented by short low pulse in the middle of a bit time remaining idle high for a 1 for inverted polarity.
0 Normal polarity
1 Inverted polarity
Break Transmit Character Length — This bit determines whether the transmit break character is 10 or 11 bit
respectively 13 or 14 bits long. The detection of a framing error is not affected by this bit.
0 Break character is 10 or 11 bit long
1 Break character is 13 or 14 bit long
Transmitter Pin Data Direction in Single-Wire Mode — This bit determines whether the TXD pin is going to
be used as an input or output, in the single-wire mode of operation. This bit is only relevant in the single-wire
mode of operation.
0 TXD pin to be used as an input in single-wire mode
1 TXD pin to be used as an output in single-wire mode
Receiver Active Flag — RAF is set when the receiver detects a logic 0 during the RT1 time period of the start
bit search. RAF is cleared when the receiver detects an idle character.
0 No reception in progress
1 Reception in progress
MC9S12HZ256 Data Sheet, Rev. 2.04
398
Freescale Semiconductor