MC9S12HZ256 Datasheet, PDF (604/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 22 Module Mapping Control (MMCV4)
22.1.1 Features
• Registers for mapping of address space for on-chip RAM, EEPROM, and FLASH (or ROM)
memory blocks and associated registers
• Memory mapping control and selection based upon address decode and system operating mode
• Core address bus control
• Core data bus control and multiplexing
• Core security state decoding
• Emulation chip select signal generation (ECS)
• External chip select signal generation (XCS)
• Internal memory expansion
• External stretch and ROM mapping control functions via the MISC register
• Reserved registers for test purposes
• Configurable system memory options defined at integration of core into the system-on-a-chip
(SoC).
22.1.2 Modes of Operation
Some of the registers operate differently depending on the mode of operation (i.e., normal expanded wide,
special single chip, etc.). This is best understood from the register descriptions.
22.2 External Signal Description
All interfacing with the MMC sub-block is done within the core, it has no external signals.
22.3 Memory Map and Register Definition
A summary of the registers associated with the MMC sub-block is shown in Figure 22-2. Detailed
descriptions of the registers and bits are given in the subsections that follow.
22.3.1 Module Memory Map
Table 22-1. MMC Memory Map
Address
Offset
Register
Initialization of Internal RAM Position Register (INITRM)
Initialization of Internal Registers Position Register (INITRG)
Initialization of Internal EEPROM Position Register (INITEE)
Miscellaneous System Control Register (MISC)
Reserved
.
.
.
.
Access
R/W
R/W
R/W
R/W
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MC9S12HZ256 Data Sheet, Rev. 2.04
604
Freescale Semiconductor