MC9S12HZ256 Datasheet, PDF (468/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
15.4.2.4 PWM Timer Counters
Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source
(reference Figure 15-34 for the available clock sources and rates). The counter compares to two registers,
a duty register and a period register as shown in Figure 15-35. When the PWM counter matches the duty
register the output flip-flop changes state causing the PWM waveform to also change state. A match
between the PWM counter and the period register behaves differently depending on what output mode is
selected as shown in Figure 15-35 and described in Section 15.4.2.5, “Left Aligned Outputs,” and
Section 15.4.2.6, “Center Aligned Outputs.”
Each channel counter can be read at anytime without affecting the count or the operation of the PWM
channel.
Any value written to the counter causes the counter to reset to 0x0000, the counter direction to be set to
up, the immediate load of both duty and period registers with values from the buffers, and the output to
change according to the polarity bit. When the channel is disabled (PWMEx = 0), the counter stops. When
a channel becomes enabled (PWMEx = 1), the associated PWM counter continues from the count in the
PWMCNTx register. This allows the waveform to resume when the channel is re-enabled. When the
channel is disabled, writing 0 to the period register will cause the counter to reset on the next selected
clock.
NOTE
If the user wants to start a new “clean” PWM waveform without any
“history” from the old waveform, the user must write to channel counter
(PWMCNTx) prior to enabling the PWM channel (PWMEx = 1).
Generally, writes to the counter are done prior to enabling a channel to start from a known state. However,
writing a counter can also be done while the PWM channel is enabled (counting). The effect is similar to
writing the counter when the channel is disabled except that the new period is started immediately with
the output set according to the polarity bit.
NOTE
Writing to the counter while the channel is enabled can cause an irregular
PWM cycle to occur.
The counter is cleared at the end of the effective period (see Section 15.4.2.5, “Left Aligned Outputs,” and
Section 15.4.2.6, “Center Aligned Outputs,” for more details).
Table 15-11. PWM Timer Counter Conditions
Counter Clears (0x0000)
When PWMCNTx register
written to any value
Effective period ends
Counter Counts
Counter Stops
When PWM channel is
enabled (PWMEx = 1). Counts
from last value in PWMCNTx.
When PWM channel is
disabled (PWMEx = 0)
MC9S12HZ256 Data Sheet, Rev. 2.04
468
Freescale Semiconductor