MC9S12HZ256 Datasheet, PDF (403/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 13 Serial Communication Interface (SCIV4)
13.4.3 Baud Rate Generation
A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the
transmitter. The value from 0 to 8191 written to the SBR[12:0] bits determines the module clock divisor.
The SBR bits are in the SCI baud rate registers (SCIBDH and SCIBDL). The baud rate clock is
synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the
transmitter. The receiver has an acquisition rate of 16 samples per bit time.
Baud rate generation is subject to one source of error:
• Integer division of the module clock may not give the exact target frequency.
Table 13-13 lists some examples of achieving target baud rates with a module clock frequency of 10.2
MHz.
When IREN = 0 then,
SCI baud rate = SCI module clock / (16 * SCIBR[12:0])
Table 13-13. Baud Rates (Example: Module Clock = 10.2 MHz)
Bits
SBR[12–0]
17
33
66
133
266
531
1062
2125
4250
5795
Receiver
Clock (Hz)
600,000.0
309,090.9
154,545.5
76,691.7
38,345.9
19,209.0
9604.5
4800.0
2400.0
1760.1
Transmitter
Clock (Hz)
37,500.0
19,318.2
9659.1
4793.2
2396.6
1200.6
600.3
300.0
150.0
110.0
Target Baud
Rate
38,400
19,200
9600
4800
2400
1200
600
300
150
110
Error
(%)
2.3
.62
.62
.14
.14
.11
.05
.00
.00
.00
MC9S12HZ256 Data Sheet, Rev. 2.04
Freescale Semiconductor
403