MC9S12HZ256 Datasheet, PDF(518/692 Page) Freescale Semiconductor, Inc – HCS12 Microcontrollers

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MC9S12HZ256 Datasheet, PDF (518/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

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Chapter 18 Background Debug Module (BDMV4)

18.4 Functional Description

The BDM receives and executes commands from a host via a single wire serial interface. There are two

types of BDM commands, namely, hardware commands and ï¬rmware commands.

Hardware commands are used to read and write target system memory locations and to enter active

background debug mode, see Section 18.4.3, âBDM Hardware Commands.â Target system memory

includes all memory that is accessible by the CPU.

Firmware commands are used to read and write CPU resources and to exit from active background debug

mode, see Section 18.4.4, âStandard BDM Firmware Commands.â The CPU resources referred to are the

accumulator (D), X index register (X), Y index register (Y), stack pointer (SP), and program counter (PC).

Hardware commands can be executed at any time and in any mode excluding a few exceptions as

highlighted, see Section 18.4.3, âBDM Hardware Commands.â Firmware commands can only be executed

when the system is in active background debug mode (BDM).

18.4.1 Security

If the user resets into special single-chip mode with the system secured, a secured mode BDM ï¬rmware

lookup table is brought into the map overlapping a portion of the standard BDM ï¬rmware lookup table.

The secure BDM ï¬rmware veriï¬es that the on-chip EEPROM and FLASH EEPROM are erased. This

being the case, the UNSEC bit will get set. The BDM program jumps to the start of the standard BDM

ï¬rmware and the secured mode BDM ï¬rmware is turned off and all BDM commands are allowed. If the

EEPROM or FLASH do not verify as erased, the BDM ï¬rmware sets the ENBDM bit, without asserting

UNSEC, and the ï¬rmware enters a loop. This causes the BDM hardware commands to become enabled,

but does not enable the ï¬rmware commands. This allows the BDM hardware to be used to erase the

EEPROM and FLASH. After execution of the secure ï¬rmware, regardless of the results of the erase tests,

the CPU registers, INITEE and PPAGE, will no longer be in their reset state.

18.4.2 Enabling and Activating BDM

The system must be in active BDM to execute standard BDM ï¬rmware commands. BDM can be activated

only after being enabled. BDM is enabled by setting the ENBDM bit in the BDM status (BDMSTS)

register. The ENBDM bit is set by writing to the BDM status (BDMSTS) register, via the single-wire

interface, using a hardware command such as WRITE_BD_BYTE.

After being enabled, BDM is activated by one of the following1:

â¢ Hardware BACKGROUND command

â¢ BDM external instruction tagging mechanism

â¢ CPU BGND instruction

â¢ Breakpoint sub-blockâs force or tag mechanism2

When BDM is activated, the CPU ï¬nishes executing the current instruction and then begins executing the

ï¬rmware in the standard BDM ï¬rmware lookup table. When BDM is activated by the breakpoint

1. BDM is enabled and active immediately out of special single-chip reset.

2. This method is only available on systems that have a a breakpoint or a debug sub-block.

MC9S12HZ256 Data Sheet, Rev. 2.04

518

Freescale Semiconductor

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