MC9S12HZ256 Datasheet, PDF (509/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 18
Background Debug Module (BDMV4)
18.1 Introduction
This section describes the functionality of the background debug module (BDM) sub-block of the HCS12
core platform.
A block diagram of the BDM is shown in Figure 18-1.
HOST
SYSTEM
BKGD
16-BIT SHIFT REGISTER
ENTAG
BDMACT
TRACE
INSTRUCTION DECODE
AND EXECUTION
BUS INTERFACE
AND
CONTROL LOGIC
ADDRESS
DATA
CLOCKS
SDV
ENBDM
STANDARD BDM
FIRMWARE
LOOKUP TABLE
CLKSW
Figure 18-1. BDM Block Diagram
The background debug module (BDM) sub-block is a single-wire, background debug system implemented
in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD
pin.
BDMV4 has enhanced capability for maintaining synchronization between the target and host while
allowing more flexibility in clock rates. This includes a sync signal to show the clock rate and a handshake
signal to indicate when an operation is complete. The system is backwards compatible with older external
interfaces.
18.1.1 Features
• Single-wire communication with host development system
• BDMV4 (and BDM2): Enhanced capability for allowing more flexibility in clock rates
• BDMV4: SYNC command to determine communication rate
• BDMV4: GO_UNTIL command
• BDMV4: Hardware handshake protocol to increase the performance of the serial communication
• Active out of reset in special single-chip mode
MC9S12HZ256 Data Sheet, Rev. 2.04
Freescale Semiconductor
509