MC9S12HZ256 Datasheet, PDF (142/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.4.7 Port P Wired-OR Mode Register (WOMP)
7
R
0
W
6
5
4
3
2
1
0
0
0
0
WOMP5
WOMP4
WOMP2
WOMPO
Reset
0
0
0
0
0
0
0
0
= Reserved or Unimplemented
Figure 4-29. Port P Wired-OR Mode Register (WOMP)
Read: Anytime. Write: Anytime.
This register selects whether a port P output is configured as push-pull or wired-or. When a Wired-OR
Mode Register bit is set to 1, the corresponding output pin is driven active low only (open drain) and a
high level is not driven. A Wired-OR Mode Register bit has no effect if the corresponding pin is configured
as an input.
If the IIC is enabled and the corresponding PWM channels are disabled, the PP[5:4] pins are configured
as wired-or and the corresponding Wired-OR Mode Register bits have no effect.
Table 4-22. WOMP Field Descriptions
Field
Description
5:4
Wired-OR Mode Port P
WOMP[5:4] 0 Output buffers operate as push-pull outputs.
1 Output buffers operate as open-drain outputs.
2
WOMP2
Wired-OR Mode Port P
0 Output buffers operate as push-pull outputs.
1 Output buffers operate as open-drain outputs.
0
WOMP0
Wired-OR Mode Port P
0 Output buffers operate as push-pull outputs.
1 Output buffers operate as open-drain outputs.
MC9S12HZ256 Data Sheet, Rev. 2.04
142
Freescale Semiconductor