MC9S12HZ256 Datasheet, PDF (139/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

4.3.4.2 Port P Input Register (PTIP)
Chapter 4 Port Integration Module (PIM9HZ256V2)
7
R
0
W
6
5
4
3
2
0
PTIP5
PTIP4
PTIP3
PTIP2
Reset
0
0
u
u
u
u
= Reserved or Unimplemented
u = Unaffected by reset
Figure 4-24. Port P I/O Register (PTP)
Read: Anytime. Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins.
4.3.4.3 Port P Data Direction Register (DDRP)
1
PTIP1
u
0
PTIP0
u
7
R
0
W
6
5
4
3
2
1
0
0
DDRP5
DDRP4
DDRP3
DDRP2
DDRP1
DDRP0
Reset
0
0
0
0
0
0
0
0
= Reserved or Unimplemented
Figure 4-25. Port P Data Direction Register (DDRP)
Read: Anytime. Write: Anytime.
This register configures port pins PP[5:0] as either input or output.
If a PWM channel is enabled, the corresponding pin is forced to be an output and the associated Data
Direction Register bit has no effect. Channel 5 can also force the corresponding pin to be an input if the
shutdown feature is enabled.
When the IIC bus is enabled, the PP[5:4] pins become the SCL and SDA bidirectional pins respectively
as long as the corresponding PWM channels are disabled. The associated Data Direction Register bits have
no effect.
When the SCI1 transmitter is enabled, the PP[0] pin becomes the TXD1 output pin and the associated Data
Direction Register bit has no effect. When the SCI1 receiver is enabled, the PP[2] pin becomes the RXD1
input pin and the associated Data Direction Register bit has no effect.
If the PWM, IIC and SCI1 functions are disabled, the corresponding Data Direction Register bit reverts to
control the I/O direction of the associated pin.
Table 4-18. DDRP Field Descriptions
Field
5:0
Data Direction Port P
DDRP[5:0] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
Description
MC9S12HZ256 Data Sheet, Rev. 2.04
Freescale Semiconductor
139