MC9S12HZ256 Datasheet, PDF (618/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 22 Module Mapping Control (MMCV4)
Table 22-17. External/Internal Page Window Access
pag_sw1:pag_sw0
00
01
10
11
Partitioning
876K off-Chip,
128K on-Chip
768K off-chip,
256K on-chip
512K off-chip,
512K on-chip
0K off-chip,
1M on-chip
PIX5:0 Value
0x0000–0x0037
0x0038–0x003F
0x0000–0x002F
0x0030–0x003F
0x0000–0x001F
0x0020–0x003F
N/A
0x0000–0x003F
Page Window
Access
External
Internal
External
Internal
External
Internal
External
Internal
NOTE
The partitioning as defined in Table 22-17 applies only to the allocated
memory space and the actual on-chip memory sizes implemented in the
system may differ. Please refer to the device overview chapter for actual
sizes.
The PPAGE register holds the page select value for the program page window. The value of the PPAGE
register can be manipulated by normal read and write (some devices don’t allow writes in some modes)
instructions as well as the CALL and RTC instructions.
Control registers, vector spaces, and a portion of on-chip memory are located in unpaged portions of the
64K byte physical address space. The stack and I/O addresses should also be in unpaged memory to make
them accessible from any page.
The starting address of a service routine must be located in unpaged memory because the 16-bit exception
vectors cannot point to addresses in paged memory. However, a service routine can call other routines that
are in paged memory. The upper 16K byte block of memory space (0xC000–0xFFFF) is unpaged. It is
recommended that all reset and interrupt vectors point to locations in this area.
22.4.3.1 CALL and Return from Call Instructions
CALL and RTC are uninterruptable instructions that automate page switching in the program expansion
window. CALL is similar to a JSR instruction, but the subroutine that is called can be located anywhere in
the normal 64K byte address space or on any page of program expansion memory. CALL calculates and
stacks a return address, stacks the current PPAGE value, and writes a new instruction-supplied value to
PPAGE. The PPAGE value controls which of the 64 possible pages is visible through the 16K byte
expansion window in the 64K byte memory map. Execution then begins at the address of the called
subroutine.
During the execution of a CALL instruction, the CPU:
• Writes the old PPAGE value into an internal temporary register and writes the new
instruction-supplied PPAGE value into the PPAGE register.
MC9S12HZ256 Data Sheet, Rev. 2.04
618
Freescale Semiconductor