MC9S12HZ256 Datasheet, PDF (134/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.3 Port M
Port M is associated with Freescale’s scalable controller area network (CAN1 and CAN0) modules. Each
pin is assigned to these modules according to the following priority: CAN1/CAN0 > general-purpose I/O.
When the CAN1 module is enabled, PM[5:4] pins become TXCAN1 (transmitter) and RXCAN1
(receiver) pins for the CAN1 module. When the CAN0 module is enabled, PM[3:2] pins become TXCAN0
(transmitter) and RXCAN0 (receiver) pins for the CAN0 module. Refer to the MSCAN block description
chapter for information on enabling and disabling the CAN module.
During reset, port M pins are configured as high-impedance inputs.
4.3.3.1 Port M I/O Register (PTM)
7
6
5
4
3
2
1
0
R
0
0
0
0
PTM5
PTM4
PTM3
PTM2
W
CAN0/CAN1:
TXCAN1 RXCAN1 TXCAN0 RXCAN0
Reset
0
0
0
0
0
0
0
0
= Reserved or Unimplemented
Figure 4-16. Port M I/O Register (PTM)
Read: Anytime. Write: Anytime.
If the associated data direction bit (DDRMx) is set to 1 (output), a read returns the value of the I/O register
bit. If the associated data direction bit (DDRMx) is set to 0 (input), a read returns the value of the pin.
4.3.3.2 Port M Input Register (PTIM)
7
6
5
4
3
2
1
0
R
0
0
PTIM5
PTIM4
PTIM3
PTIM2
0
0
W
Reset
0
0
u
u
u
u
0
0
= Reserved or Unimplemented
u = Unaffected by reset
Figure 4-17. Port M Input Register (PTIM)
Read: Anytime. Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins.
MC9S12HZ256 Data Sheet, Rev. 2.04
134
Freescale Semiconductor