MC9S12HZ256 Datasheet, PDF (450/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
Table 15-4. PWMCLK Field Descriptions (continued)
Field
2
PCLK2
1
PCLK1
0
PCLK0
Description
Pulse Width Channel 2 Clock Select
0 Clock B is the clock source for PWM channel 2.
1 Clock SB is the clock source for PWM channel 2.
Pulse Width Channel 1 Clock Select
0 Clock A is the clock source for PWM channel 1.
1 Clock SA is the clock source for PWM channel 1.
Pulse Width Channel 0 Clock Select
0 Clock A is the clock source for PWM channel 0.
1 Clock SA is the clock source for PWM channel 0.
15.3.2.4 PWM Prescale Clock Select Register (PWMPRCLK)
This register selects the prescale clock source for clocks A and B independently.
7
6
5
4
3
2
1
R
0
0
PCKB2
PCKB1
PCKB0
PCKA2
PCKA1
W
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 15-6. PWM Prescaler Clock Select Register (PWMPRCLK)
Read: anytime
Write: anytime
NOTE
PCKB2–PCKB0 and PCKA2–PCKA0 register bits can be written anytime.
If the clock prescale is changed while a PWM signal is being generated, a
truncated or stretched pulse can occur during the transition.
0
PCKA0
0
Table 15-5. PWMPRCLK Field Descriptions
Field
Description
6:5
Prescaler Select for Clock B — Clock B is 1 of two clock sources which can be used for channels 2 or 3. These
PCKB[2:0] three bits determine the rate of clock B, as shown in Table 15-6.
2:0
Prescaler Select for Clock A — Clock A is 1 of two clock sources which can be used for channels 0, 1, 4, or 5.
PCKA[2:0] These three bits determine the rate of clock A, as shown in Table 15-7.
MC9S12HZ256 Data Sheet, Rev. 2.04
450
Freescale Semiconductor