MC9S12HZ256 Datasheet, PDF (641/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Appendix A Electrical Characteristics
Table A-14. Voltage Regulator - Capacitive Loads
Num
Characteristic
1 VDD external capacitive load
3 VDDPLL external capacitive load
Symbol
Min
C_DDext
200
C_DDPLLext
90
Typical
440
220
Max
Unit
12000
nF
5000
nF
A.5 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).
A.5.1 Startup
Table A-15 summarizes several startup characteristics explained in this section. Detailed description of the
startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.
Table A-15. Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
1 T POR release level
2 T POR assert level
3 D Reset input pulse width, minimum input time
4 D Startup from Reset
5 D Interrupt pulse width, IRQ edge-sensitive mode
6 D Wait recovery startup time
V_PORR
V_PORA
PW_RSTL
n_RST
PW_IRQ
t_WRS
0.97
2
192
20
2.07
V
V
t_osc
196
n_osc
ns
14
t_cyc
A.5.1.1 POR
The release level V_PORR and the assert level V_PORA are derived from the VDD supply. They are also valid
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time t_CQOUT no valid oscillation is detected, the MCU will start using the internal self
clock. The fastest startup time possible is given by n_uposc.
A.5.1.2 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG Flags Register has not been set.
MC9S12HZ256 Data Sheet, Rev. 2.04
Freescale Semiconductor
641