MC9S12HZ256 Datasheet, PDF (435/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 14 Serial Peripheral Interface (SPIV3)
End of Idle State
SCK Edge Nr.
SCK (CPOL = 0)
Begin
Transfer
End
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Begin of Idle State
SCK (CPOL = 1)
SAMPLE I
MOSI/MISO
CHANGE O
MOSI pin
CHANGE O
MISO pin
SEL SS (O)
Master only
SEL SS (I)
tL
tT tI tL
MSB first (LSBFE = 0): MSB
LSB first (LSBFE = 1): LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB Minimum 1/2 SCK
MSB
for t_T, t_l, t_L
t_L = Minimum leading time before the first SCK edge, not required for back to back transfers
t_T = Minimum trailing time after the last SCK edge
t_I = Minimum idling time between transfers (minimum SS high time), not required for back to back transfers
Figure 14-10. SPI Clock Format 1 (CPHA = 1)
14.4.4 SPI Baud Rate Generation
Baud rate generation consists of a series of divider stages. Six bits in the SPI Baud Rate register (SPPR2,
SPPR1, SPPR0, SPR2, SPR1, and SPR0) determine the divisor to the SPI module clock which results in
the SPI baud rate.
The SPI clock rate is determined by the product of the value in the baud rate preselection bits
(SPPR2–SPPR0) and the value in the baud rate selection bits (SPR2–SPR0). The module clock divisor
equation is shown in Figure 14-11
When all bits are clear (the default condition), the SPI module clock is divided by 2. When the selection
bits (SPR2–SPR0) are 001 and the preselection bits (SPPR2–SPPR0) are 000, the module clock divisor
becomes 4. When the selection bits are 010, the module clock divisor becomes 8 etc.
When the preselection bits are 001, the divisor determined by the selection bits is multiplied by 2. When
the preselection bits are 010, the divisor is multiplied by 3, etc. See Table 14-7 for baud rate calculations
for all bit conditions, based on a 25-MHz bus clock. The two sets of selects allows the clock to be divided
by a non-power of two to achieve other baud rates such as divide by 6, divide by 10, etc.
MC9S12HZ256 Data Sheet, Rev. 2.04
Freescale Semiconductor
435