MC9S12HZ256 Datasheet, PDF (38/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 1 MC9S12HZ256 Device Overview
1.5.3 TEST — Test Pin
This pin is reserved for test.
NOTE
The TEST pin must be tied to V_SS in all applications.
1.5.4 XFC — PLL Loop Filter Pin
Dedicated pin used to create the PLL loop filter. Please ask your Freescale representative for the
interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be
avoided.
XFC
MCU
R
C_S
V_DDPLL
C_P
V_DDPLL
Figure 1-9. PLL Loop Filter Connections
1.5.5 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode
Pin
The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug
communication. In MCU expanded modes of operation when instruction tagging is on, an input low on
this pin during the falling edge of E-clock tags the high half of the instruction word being read into the
instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is
latched to the MODC bit at the rising edge of RESET.
1.5.6 Port Pins
1.5.6.1 PAD[7:0] / AN[7:0] / KWAD[7:0] — Port AD I/O Pins [7:0]
PAD7–PAD0 are general-purpose input or output pins and analog inputs for the analog-to-digital
converter. They can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.
1.5.6.2 PA[7:0] / FP[15:8] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins
PA7–PA0 are general-purpose input or output pins. They can be configured as frontplane segment driver
outputs FP15–FP8 of the LCD. In MCU expanded modes of operation, these pins are used for the
multiplexed external address and data bus.
MC9S12HZ256 Data Sheet, Rev. 2.04
38
Freescale Semiconductor