MC9S12HZ256 Datasheet, PDF (157/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

4.3.8.2 Port V Input Register (PTIV)
Chapter 4 Port Integration Module (PIM9HZ256V2)
7
R PTIV7
W
6
PTIV6
5
PTIV5
4
PTIV4
3
PTIV3
2
PTIV2
1
PTIV1
0
PTIV0
Reset
u
u
u
u
u
u
u
u
= Reserved or Unimplemented
u = Unaffected by reset
Figure 4-50. Port V Input Register (PTIV)
Read: Anytime. Write: Never, writes to this register have no effect.
If the associated slew rate control is enabled (digital input buffer is disabled), a read returns a “1”. If the
associated slew rate control is disabled (digital input buffer is enabled), a read returns the status of the
associated pin.
4.3.8.3 Port V Data Direction Register (DDRV)
R
W
Reset
7
DDRV7
0
6
DDRV6
5
DDRV5
4
DDRV4
3
DDRV3
2
DDRV2
0
0
0
0
0
Figure 4-51. Port V Data Direction Register (DDRV)
1
DDRV1
0
0
DDRV0
0
Read: Anytime. Write: Anytime.
This register configures port pins PV[7:0] as either input or output.
When enabled, the SSD or MC modules force the I/O state to be an output for each associated pin and the
associated Data Direction Register bit has no effect. If the SSD and MC modules are disabled, the
corresponding Data Direction Register bits revert to control the I/O direction of the associated pins.
Table 4-36. DDRV Field Descriptions
Field
7:0
Data Direction Port V
DDRV[7:0] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
Description
MC9S12HZ256 Data Sheet, Rev. 2.04
Freescale Semiconductor
157