MC9S12HZ256 Datasheet, PDF (539/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 19 Debug Module (DBGV1)
DBG READ DATA BUS
ADDRESS BUS
WRITE DATA BUS
READ DATA BUS
READ/WRITE
DBG MODE ENABLE
CHANGE-OF-FLOW
INDICATORS
MCU IN BDM
CPU PROGRAM COUNTER
INSTRUCTION
LAST CYCLE
BUS CLOCK
REGISTER
WRITE DATA BUS
M
U
READ DATA BUS
X
ADDRESS/DATA/CONTROL
REGISTERS
COMPARATOR A
COMPARATOR B
COMPARATOR C
CONTROL
MATCH_A
MATCH_B
MATCH_C
LOOP1
TRACER
BUFFER
CONTROL
LOGIC
TAG
FORCE
DETAIL
EVENT ONLY
STORE
POINTER
M
U
M
X
U
X
LAST
INSTRUCTION
ADDRESS
64 x 16 BIT
WORD
TRACE
BUFFER
PROFILE
CAPTURE
REGISTER
PROFILE CAPTURE MODE
TRACE BUFFER
M
OR PROFILING DATA
U
X
READ/WRITE
Figure 19-2. DBG Block Diagram in DBG Mode
19.2 External Signal Description
The DBG sub-module relies on the external bus interface (generally the MEBI) when the DBG is matching
on the external bus.
The tag pins in Table 19-1 (part of the MEBI) may also be a part of the breakpoint operation.
Table 19-1. External System Pins Associated with DBG and MEBI
Pin Name
Pin Functions
Description
BKGD/MODC/
TAGHI
PE3/LSTRB/ TAGLO
TAGHI
TAGLO
When instruction tagging is on, a 0 at the falling edge of E tags the high half of the
instruction word being read into the instruction queue.
In expanded wide mode or emulation narrow modes, when instruction tagging is on
and low strobe is enabled, a 0 at the falling edge of E tags the low half of the
instruction word being read into the instruction queue.
MC9S12HZ256 Data Sheet, Rev. 2.04
Freescale Semiconductor
539