MC9S12HZ256 Datasheet, PDF (301/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 10 Stepper Stall Detector (SSDV1)
10.3.2.6 Integration Accumulator Register (ITGACC)
15
14
13
12
11
10
9
8
R
ITGACC
W
Reset
0
0
0
0
0
0
0
0
Figure 10-8. Integration Accumulator Register High (ITGACC)
7
6
5
4
3
2
1
0
R
ITGACC
W
Reset
0
0
0
0
0
0
0
0
Read: anytime.
Figure 10-9. Integration Accumulator Register Low (ITGACC)
Write: Never.
NOTE
A separate read for high byte and low byte gives a different result than
accessing the register as a word.
This 16-bit field is signed and is represented in two’s complement. It indicates the change in flux while
integrating the back EMF present in the non-driven coil during a return to zero event.
When ITG is zero, the accumulator is initialized to 0x0000 and the sigma-delta converter is in a reset state.
When ITG is one, the accumulator increments or decrements depending on the sigma-delta conversion
sample. The accumulator sample frequency is determined by the ACLKS field. The accumulator freezes
at 0x7FFF on a positive overflow and freezes at 0x8000 on a negative overflow.
10.4 Functional Description
The stepper stall detector (SSD) has a simple control block to configure the H-bridge drivers of a stepper
motor in four different full step states with four available modes during a return to zero event. The SSD
has a detect circuit using a sigma-delta converter to measure and integrate changes in flux of the
de-energized winding in the stepping motor and the conversion result is accumulated in a 16-bit signed
register. The SSD also has a 16-bit modulus down counter to monitor blanking and integration times. DC
offset compensation is implemented when using the modulus down counter to monitor integration times.
10.4.1 Return to Zero Modes
There are four return to zero modes as shown in Table 10-11.
Table 10-11. Return to Zero Modes
ITG DCOIL
Mode
MC9S12HZ256 Data Sheet, Rev. 2.04
Freescale Semiconductor
301