MC9S12HZ256 Datasheet, PDF (101/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

All bits read 0 and are not writable.
Chapter 3 2 Kbyte EEPROM Module (EETS2KV1)
3.3.2.4 EEPROM Configuration Register (ECNFG)
The ECNFG register enables the EEPROM interrupts.
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
CBEIE
CCIE
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 3-7. EEPROM Configuration Register (ECNFG)
CBEIE and CCIE bits are readable and writable while bits 5-0 read 0 and are not writable.
Table 3-4. ECNFG Field Descriptions
Field
7
CBEIE
6
CCIE
Description
Command Buffer Empty Interrupt Enable — The CBEIE bit enables the interrupts in case of an empty
command buffer in the EEPROM.
0 Command buffer empty interrupts disabled.
1 An interrupt will be requested whenever the CBEIF flag is set (see Section 3.3.2.6, “EEPROM Status Register
(ESTAT)”).
Command Complete Interrupt Enable — The CCIE bit enables the interrupts in case of all commands being
completed in the EEPROM.
0 Command complete interrupts disabled.
1 An interrupt will be requested whenever the CCIF flag is set (see Section 3.3.2.6, “EEPROM Status Register
(ESTAT)”).
3.3.2.5 EEPROM Protection Register (EPROT)
The EPROT register defines which EEPROM sectors are protected against program or erase.
7
6
5
4
3
2
1
0
R
NV6
NV5
NV4
EPOPEN
EPDIS
EP2
EP1
EP0
W
Reset
F
F
F
F
F
F
F
F
= Unimplemented or Reserved
Figure 3-8. EEPROM Protection Register (EPROT)
The EPROT register is loaded from EEPROM array address 0x07FD during reset, as indicated by the F in
Figure 3-8.
All bits in the EPROT register are readable. Bits NV[6:4] are not writable. The EPOPEN and EPDIS bits
in the EPROT register can only be written to the protected state (i.e., 0). The EP[2:0] bits can be written
anytime until bit EPDIS is cleared. If the EPOPEN bit is cleared, then the state of the EPDIS and EP[2:0]
bits is irrelevant.
MC9S12HZ256 Data Sheet, Rev. 2.04
Freescale Semiconductor
101