MC9S12HZ256 Datasheet, PDF (517/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 18 Background Debug Module (BDMV4)
18.3.2.2 BDM CCR Holding Register (BDMCCR)
7
R
CCR7
W
6
CCR6
5
CCR5
4
CCR4
3
CCR3
2
CCR2
1
CCR1
0
CCR0
Reset
0
0
0
0
0
0
0
0
Read: All modes
Figure 18-4. BDM CCR Holding Register (BDMCCR)
Write: All modes
NOTE
When BDM is made active, the CPU stores the value of the CCR register in
the BDMCCR register. However, out of special single-chip reset, the
BDMCCR is set to 0xD8 and not 0xD0 which is the reset value of the CCR
register.
When entering background debug mode, the BDM CCR holding register is used to save the contents of the
condition code register of the user’s program. It is also used for temporary storage in the standard BDM
firmware mode. The BDM CCR holding register can be written to modify the CCR value.
18.3.2.3 BDM Internal Register Position Register (BDMINR)
7
6
5
4
3
2
1
0
R
0
REG14
REG13
REG12
REG11
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Read: All modes
Figure 18-5. BDM Internal Register Position (BDMINR)
Write: Never
Table 18-4. BDMINR Field Descriptions
Field
Description
6:3
Internal Register Map Position — These four bits show the state of the upper five bits of the base address for
REG[14:11] the system’s relocatable register block. BDMINR is a shadow of the INITRG register which maps the register
block to any 2K byte space within the first 32K bytes of the 64K byte address space.
MC9S12HZ256 Data Sheet, Rev. 2.04
Freescale Semiconductor
517