MC9S12HZ256 Datasheet, PDF(506/692 Page) Freescale Semiconductor, Inc – HCS12 Microcontrollers

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MC9S12HZ256 Datasheet, PDF (506/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

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Chapter 17 Dual Output Voltage Regulator (VREG3V3V2)

The regulator is a linear series regulator with a bandgap reference in its Full Performance Mode and a

voltage clamp in Reduced Power Mode. All load currents flow from input VDDR to VSS or VSSPLL, the

reference circuits are connected to VDDA and VSSA.

17.4.2 Full-Performance Mode

In Full Performance Mode, a fraction of the output voltage (VDD) and the bandgap reference voltage are

fed to an operational amplifier. The amplified input voltage difference controls the gate of an output driver

which basically is a large NMOS transistor connected to the output.

17.4.3 Reduced-Power Mode

In Reduced Power Mode, the driver gate is connected to a buffered fraction of the input voltage (VDDR).

The operational amplifier and the bandgap are disabled to reduce power consumption.

17.4.4 LVD â Low-Voltage Detect

sub-block LVD is responsible for generating the low-voltage interrupt (LVI). LVD monitors the input

voltage (VDDAâVSSA) and continuously updates the status flag LVDS. Interrupt flag LVIF is set whenever

status flag LVDS changes its value. The LVD is available in FPM and is inactive in Reduced Power Mode

and Shutdown Mode.

17.4.5 POR â Power-On Reset

This functional block monitors output VDD. If VDD is below VPORD, signal POR is high, if it exceeds

VPORD, the signal goes low. The transition to low forces the CPU in the power-on sequence.

Due to its role during chip power-up this module must be active in all operating modes of VREG3V3.

17.4.6 LVR â Low-Voltage Reset

Block LVR monitors the primary output voltage VDD. If it drops below the assertion level (VLVRA) signal

LVR asserts and when rising above the deassertion level (VLVRD) signal LVR negates again. The LVR

function is available only in Full Performance Mode.

17.4.7 CTRL â Regulator Control

This part contains the register block of VREG3V3 and further digital functionality needed to control the

operating modes. CTRL also represents the interface to the digital core logic.

MC9S12HZ256 Data Sheet, Rev. 2.04

506

Freescale Semiconductor

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