MC9S12HZ256 Datasheet, PDF (72/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
FPROT register reflect the active protection scenario. See the FPHS and FPLS descriptions for additional
restrictions.
Table 2-15. Flash Protection Scenario Transitions
From
To Protection Scenario¹
Protection
Scenario
0
1
2
3
4
5
6
7
0
X
X
X
X
1
X
X
2
X
X
3
X
4
X
X
5
X
X
X
X
6
X
X
X
X
7
X
X
X
X
X
X
X
X
1 _{Allowed transitions marked with X.}
2.3.2.7 Flash Status Register (FSTAT)
The banked FSTAT register defines the operational status of the module.
7
6
5
4
3
2
1
0
R
CCIF
0
BLANK
0
0
CBEIF
PVIOL
ACCERR
W
Reset
1
1
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-10. Flash Status Register (FSTAT - Normal Mode)
7
6
5
4
3
2
1
0
R
CCIF
0
BLANK
0
CBEIF
PVIOL
ACCERR
FAIL
W
Reset
1
1
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-11. Flash Status Register (FSTAT - Special Mode)
CBEIF, PVIOL, and ACCERR are readable and writable, CCIF and BLANK are readable and not writable,
remaining bits read 0and are not writable in normal mode. FAIL is readable and writable in special mode.
FAIL must be clear when starting a command write sequence.
MC9S12HZ256 Data Sheet, Rev. 2.04
72
Freescale Semiconductor