MC9S12HZ256 Datasheet, PDF (407/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 13 Serial Communication Interface (SCIV4)
TDRE flag is set and immediately before writing the next byte to the SCI
data register.
If the TE bit is clear and the transmission is complete, the SCI is not the
master of the TXD pin
13.4.5 Receiver
INTERNAL BUS
SBR12–SBR0
SCI DATA REGISTER
SCRXD
BUS
CLOCK
RXPOL
BAUD
DIVIDER
DATA
RECOVERY
11-BIT RECEIVE SHIFT REGISTER
H8 7 6 5 4 3 2 1 0 L
FROM TXD PIN
LOOP
OR TRANSMITTER ^CONTROL
RE
RAF
LOOPS
M
FE
RSRC
WAKE
ILT
WAKEUP
LOGIC
NF
PE
PE
PARITY
R8
PT
CHECKING
IDLE INTERRUPT REQUEST
RDRF/OR INTERRUPT REQUEST
IDLE
ILIE
RIE
RDRF
OR
Figure 13-14. SCI Receiver Block Diagram
RWU
13.4.5.1 Receiver Character Length
The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI
control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in
SCI data register high (SCIDRH) is the ninth bit (bit 8).
13.4.5.2 Character Reception
During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data
register is the read-only buffer between the internal data bus and the receive shift register.
After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the
SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set,
MC9S12HZ256 Data Sheet, Rev. 2.04
Freescale Semiconductor
407