MC9S12HZ256 Datasheet, PDF (504/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 17 Dual Output Voltage Regulator (VREG3V3V2)
17.2.3 V_DD, V_SS — Regulator Output1 (Core Logic)
Signals V_DD/V_SS are the primary outputs of VREG3V3 that provide the power supply for the core logic.
These signals are connected to device pins to allow external decoupling capacitors (100 nF...220 nF, X7R
ceramic).
In Shutdown Mode an external supply at V_DD/V_SS can replace the voltage regulator.
17.2.4 V_DDPLL, V_SSPLL — Regulator Output2 (PLL)
Signals V_DDPLL/V_SSPLL are the secondary outputs of VREG3V3 that provide the power supply for the
PLL and oscillator. These signals are connected to device pins to allow external decoupling capacitors
(100 nF...220 nF, X7R ceramic).
In Shutdown Mode an external supply at V_DDPLL/V_SSPLL can replace the voltage regulator.
17.2.5 V_REGEN — Optional Regulator Enable
This optional signal is used to shutdown VREG3V3. In that case V_DD/V_SS and V_DDPLL/V_SSPLL must be
provided externally. Shutdown Mode is entered with V_REGEN being low. If V_REGEN is high, the
VREG3V3 is either in Full Performance Mode or in Reduced Power Mode.
For the connectivity of V_REGEN see device overview chapter.
NOTE
Switching from FPM or RPM to shutdown of VREG3V3 and vice versa is
not supported while the MCU is powered.
17.3 Memory Map and Register Definition
This subsection provides a detailed description of all registers accessible in VREG3V3.
17.3.1 Module Memory Map
Figure 17-2 provides an overview of all used registers.
Table 17-2. VREG3V3 Memory Map
Address
Offset
0x0000
Use
VREG3V3 Control Register (VREGCTRL)
Access
R/W
MC9S12HZ256 Data Sheet, Rev. 2.04
504
Freescale Semiconductor