EP2S130F1020I4 Datasheet, PDF (80/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

PLLs & Clock Networks
Figure 2–42. Global & Regional Clock Connections from Corner Clock Pins &
Fast PLL Outputs Note (1)
Note to Figure 2–42:
(1) The corner fast PLLs can also be driven through the global or regional clock
networks. The global or regional clock input can be driven by an output from
another PLL, a pin-driven dedicated global or regional clock, or through a clock
control block, provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated
global signal cannot drive the PLL.
2–62
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007