EP2S130F1020I4 Datasheet, PDF (427/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

External Memory Interfaces in Stratix II and Stratix II GX Devices
Figure 3–12. DQS Update Enable Waveform
DLL Counter Update
(Every Eight Cycles)
System Clock
DQS Delay Settings
(Updated every 8 cycles)
6 bit
Update Enable
Circuitry Output
DLL Counter Update
(Every Eight Cycles)
f
DQS Postamble Circuitry
For external memory interfaces that use a bidirectional read strobe like
DDR and DDR2 SDRAM, the DQS signal is low before going to or coming
from a high-impedance state. See Figure 3–3. The state where DQS is low,
just after a high-impedance state, is called the preamble and the state
where DQS is low, just before it returns to a high-impedance state, is
called the postamble. There are preamble and postamble specifications
for both read and write operations in DDR and DDR2 SDRAM. The DQS
postamble circuitry ensures data is not lost when there is noise on the
DQS line at the end of a read postamble time. It is to be used with one of
the DQS IOE input registers such that the DQS postamble control signal
can ground the shifted DQS signal used to clock the DQ input registers at
the end of a read operation. This ensures that any glitches on the DQS
input signals at the end of the read postamble time do not affect the DQ
IOE registers.
See AN 327: Interfacing DDR SDRAM with Stratix II Devices and AN 328:
Interfacing DDR2 SDRAM with Stratix II Devices for more details.
DDR Registers
Each IOE in a Stratix II or Stratix II GX device contains six registers and
one latch. Two registers and a latch are used for input, two registers are
used for output, and two registers are used for output enable control. The
second output enable register provides the write preamble for the DQS
strobe in the DDR external memory interfaces. This active low output
enable register extends the high-impedance state of the pin by a half clock
cycle to provide the external memory’s DQS write preamble time
specification. Figure 3–13 shows the six registers and the latch in the
Stratix II or Stratix II GX IOE and Figure 3–14 shows how the second OE
register extends the DQS high-impedance state by half a clock cycle
during a write operation.
Altera Corporation
January 2008
3–31
Stratix II Device Handbook, Volume 2