EP2S130F1020I4 Datasheet, PDF (387/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
Figure 2–16. Stratix II and Stratix II GX Read/Write Clock Mode Note (1)
6 LAB Row
Clocks
6
data[ ]
DQ
ENA
Memory Block
256 ´ 16
Data In _{512 ´ 8}
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
rdaddress[ ]
DQ
ENA
Read Address
byteena[ ]
DQ
ENA
Data Out
Byte Enable
DQ
ENA
wraddress[ ]
rd_addressstall
wr_addressstall
rden (2)
wren
rdclocken
wrclocken
wrclock
rdclock
DQ
ENA
Write Address
Read Address
Clock Enable
Write Address
Clock Enable
DQ
ENA
Read Enable
Write Enable
DQ
ENA
Write
Pulse
Generator
To MultiTrack
Interconnect (3)
Notes to Figure 2–16:
(1) Violating the setup or hold time on the memory block address registers could corrupt the memory contents. This
applies to both read and write operations.
(2) The read enable rden signal is not available in the M-RAM block. An M-RAM block in simple dual-port mode is
always reading the data stored at the current read address location.
(3) Refer to the Stratix II Device Family Data Sheet (volume 1) of the Stratix II Device Handbook or the Stratix II GX Device
Family Data Sheet (volume 1) of the Stratix II GX Device Handbook for more information on the MultiTrack
interconnect.
Altera Corporation
January 2008
2–27
Stratix II Device Handbook, Volume 2