EP2S130F1020I4 Datasheet, PDF (448/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Stratix II and Stratix II GX I/O Standards Support
Figure 4–7. 1.5-V HSTL Class I Termination
Output Buffer
V_TT = 0.75 V
Z = 50 Ω
50 Ω
V_REF = 0.75 V
Input Buffer
Figure 4–8. 1.5-V HSTL Class II Termination
V_TT = 0.75 V
V_TT = 0.75 V
Output Buffer
50 Ω
50 Ω
Z = 50 Ω
V_REF = 0.75 V
Input Buffer
1.2-V HSTL
Although there is no EIA/JEDEC standard available for the 1.2-V HSTL
standard, Altera supports it for applications that operate in the 0.0 to
1.2-V HSTL logic nominal switching range. 1.2-V HSTL can be terminated
through series or parallel on-chip termination (OCT). Figure 4–9 shows
the termination scheme.
Figure 4–9. 1.2-V HSTL Termination
Output Buffer
OCT
Z = 50 Ω
V_REF = 0.6 V
Input Buffer
Differential I/O Standards
Differential I/O standards are used to achieve even faster data rates with
higher noise immunity. Apart from LVDS, LVPECL, and HyperTransport
technology, Stratix II and Stratix II GX devices also support differential
versions of SSTL and HSTL standards.
4–10
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008