EP2S130F1020I4 Datasheet, PDF (213/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

DC & Switching Characteristics
The maximum clock toggle rate is different from the maximum data bit
rate. If the maximum clock toggle rate on a regular I/O pin is 300 MHz,
the maximum data bit rate for dual data rate (DDR) could be potentially
as high as 600 Mbps on the same I/O pin.
Table 5–77 specifies the maximum input clock toggle rates. Table 5–78
specifies the maximum output clock toggle rates at 0pF load. Table 5–79
specifies the derating factors for the output clock toggle rate for a non 0pF
load.
To calculate the output toggle rate for a non 0pF load, use this formula:
The toggle rate for a non 0pF load
= 1000 / (1000/ toggle rate at 0pF load + derating factor * load value
in pF /1000)
For example, the output toggle rate at 0pF load for SSTL-18 Class II 20mA
I/O standard is 550 MHz on a -3 device clock output pin. The derating
factor is 94ps/pF. For a 10pF load the toggle rate is calculated as:
1000 / (1000/550 + 94 × 10 /1000) = 363 (MHz)
Tables 5–77 through 5–79 show the I/O toggle rates for Stratix II
devices.
Table 5–77. Maximum Input Toggle Rate on Stratix II Devices (Part 1 of 2)
Input I/O Standard
LVTTL
2.5-V LVTTL/CMOS
1.8-V LVTTL/CMOS
1.5-V LVTTL/CMOS
LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
Column I/O Pins (MHz) Row I/O Pins (MHz)
-3 -4
-5
-3 -4
-5
500 500 450 500 500 450
500 500 450 500 500 450
500 500 450 500 500 450
500 500 450 500 500 450
500 500 450 500 500 450
500 500 500 500 500 500
500 500 500 500 500 500
500 500 500 500 500 500
500 500 500 500 500 500
500 500 500 500 500 500
500 500 500 500 500 500
500 500 500 500 500 500
Dedicated Clock Inputs
(MHz)
-3
-4 -5
500 500 400
500 500 400
500 500 400
500 500 400
500 500 400
500 500 500
500 500 500
500 500 500
500 500 500
500 500 500
500 500 500
500 500 500
Altera Corporation
April 2011
5–67
Stratix II Device Handbook, Volume 1