EP2S130F1020I4 Datasheet, PDF (113/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Stratix II Architecture
Table 2–19. Board Design Recommendations for nCEO
nCE Input Buffer Power in I/O
Bank 3
Stratix II nCEO V_CCIO Voltage Level in I/O Bank 7
V_{C C I O} =
3.3 V
V_{C C I O} =
2.5 V
V_{C C I O} =
1.8 V
V_{C C I O} =
1.5 V
V_{C C I O} =
1.2 V
VCCSEL high
(V_{C C I O} Bank 3 = 1.5 V)
VCCSEL high
(V_{C C I O} Bank 3 = 1.8 V)
VCCSEL low
(nCE Powered by V_{C C P D} = 3.3V)
v(1), (2)
v (1), (2)
v
v (3), (4)
v (3), (4)
v (4)
v (5)
v
v (6)
v
v
v
Level shifter
required
Level shifter Level shifter
required
required
Notes to Table 2–19:
(1) Input buffer is 3.3-V tolerant.
(2) The nCEO output buffer meets V_{O H} (MIN) = 2.4 V.
(3) Input buffer is 2.5-V tolerant.
(4) The nCEO output buffer meets V_OH (MIN) = 2.0 V.
(5) Input buffer is 1.8-V tolerant.
(6) An external 250-Ω pull-up resistor is not required, but recommended if signal levels on the board are not optimal.
For JTAG chains, the TDO pin of the first device drives the TDI pin of the
second device in the chain. The V_CCSEL input on JTAG input I/O cells
(TCK, TMS, TDI, and TRST) is internally hardwired to GND selecting the
3.3-V/2.5-V input buffer powered by V_CCPD. The ideal case is to have the
V_CCIO of the TDO bank from the first device to match the V_CCSEL settings
for TDI on the second device, but that may not be possible depending on
the application. Table 2–20 contains board design recommendations to
ensure proper JTAG chain operation.
Table 2–20. Supported TDO/TDI Voltage Combinations (Part 1 of 2)
Device
Stratix II
TDI Input
Stratix II TDO V_{C C I O} Voltage Level in I/O Bank 4
Buffer Power _{VC C I O = 3.3 V VC C I O = 2.5 V VC C I O = 1.8 V VC C I O = 1.5 V VC C I O = 1.2 V}
Always
V_{C C P D} (3.3V)
v (1)
v (2)
v (3)
Level shifter Level shifter
required
required
Altera Corporation
May 2007
2–95
Stratix II Device Handbook, Volume 1