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EP2S130F1020I4 Datasheet, PDF (328/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1 | |||
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Clocking
Regional Clock Network
Eight regional clock networks within each quadrant of the Stratix II and
Stratix II GX device are driven by the dedicated CLK[15..0]input pins
or from PLL outputs. The regional clock networks only pertain to the
quadrant they drive into. The regional clock networks provide the lowest
clock delay and skew for logic contained within a single quadrant.
Internal logic can also drive the regional clock networks for internally
generated regional clocks and asynchronous clears, clock enables, or
other control signals with large fanout.The CLK clock pins symmetrically
drive the RCLK networks within a particular quadrant, as shown in
Figure 1â40. Refer to Table 1â18 on page 1â67 and Table 1â19 on
page 1â68 for RCLK connections from CLK pins and PLLs.
Figure 1â40. Regional Clocking Note (1)
CLK12-15
11 5
7
10
RCLK28-31 RCLK24-27
1
CLK0 -3 2
RCLK0-3
RCLK4-7
Q1 Q2
Q4 Q3
RCLK20-23
4
3
RCLK16-19
CLK8-11
RCLK8-11 RCLK12-15
8
9
12 6
CLK4-7
Note to Figure 1â40:
(1) Stratix II GX devices do not have PLLs 3, 4, 9, and 10 or clock pins 8, 9, 10, and 11.
Clock Sources Per Region
Each Stratix II and Stratix II GX device has 16 global clock networks and
32 regional clock networks that provide 48 unique clock domains for the
entire device. There are 24 unique clocks available in each quadrant
(16 global clocks and 8 regional clocks) as the input resources for registers
(see Figure 1â41).
1â64
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009
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