EP2S130F1020I4 Datasheet, PDF (309/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

PLLs in Stratix II and Stratix II GX Devices
Figure 1–26. Open- and Closed-Loop Response Bode Plots
Open-Loop Reponse Bode Plot
0 dB
Gain
Increasing the PLL's
bandwidth in effect pushes
the open loop response out.
Closed-Loop Reponse Bode Plot
Gain
Frequency
Frequency
A high-bandwidth PLL provides a fast lock time and tracks jitter on the
reference clock source, passing it through to the PLL output. A
low-bandwidth PLL filters out reference clock, but increases lock time.
Stratix II and Stratix II GX enhanced and fast PLLs allow you to control
the bandwidth over a finite range to customize the PLL characteristics for
a particular application. The programmable bandwidth feature in
Stratix II and Stratix II GX PLLs benefits applications requiring clock
switchover (e.g., TDMA frequency hopping wireless, and redundant
clocking).
Altera Corporation
July 2009
1–45
Stratix II Device Handbook, Volume 2