EP2S130F1020I4 Datasheet, PDF (506/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Differential Pin Placement Guidelines
■ Single-ended output pins must be at least one LAB row away from
differential output pins, as shown in Figure 5–20.
Figure 5–20. Single-Ended Output Pin Placement with Respect to Differential I/O Pins
Single-Ended Output Pin
Differential I/O Pin
Single_Ended Input
Single-Ended Outputs
Not Allowed
Row Boundary
DPA Usage Guidelines
The Stratix II and Stratix II GX device have differential receivers and
transmitters on the Row banks of the device. Each receiver has a
dedicated DPA circuit to align the phase of the clock to the data phase of
its associated channel. When a channel or channels of left or right banks
are used in DPA mode, the guidelines listed below must be adhered to.
Fast PLL/DPA Channel Driving Distance
■ Each fast PLL can drive up to 25 contiguous rows in DPA mode in a
single bank (not including the reference clock row). The unbonded
SERDES I/O rows are included in the 25 row calculation. These
channels can be anywhere in the bank, their distance from the PLL is
not relevant, but the channels must be within 25 rows of each other.
5–22
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008