EP2S130F1020I4 Datasheet, PDF (676/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Dedicated Remote System Upgrade Circuitry
Table 8–3. Remote System Upgrade Registers (Part 2 of 2)
Register
Update register
Status register
Description
This register contains data similar to that in the control register. However, it can only be
updated by the factory configuration by shifting data into the shift register and issuing an
update operation. When a reconfiguration cycle is triggered by the factory configuration, the
control register is updated with the contents of the update register. During a read in a factory
configuration, this register is read into the shift register.
This register is written to by the remote system upgrade circuitry on every reconfiguration to
record the cause of the reconfiguration. This information is used by the factory configuration
to determine the appropriate action following a reconfiguration. During a capture cycle, this
register is read into the shift register.
The remote system upgrade control and status registers are clocked by
the 10-MHz internal oscillator (the same oscillator that controls the user
watchdog timer). However, the remote system upgrade shift and update
registers are clocked by the user clock input (RU_CLK).
Remote System Upgrade Control Register
The remote system upgrade control register stores the application
configuration page address and user watchdog timer settings. The
control register functionality depends on the remote system upgrade
mode selection. In remote update mode, the control register page address
bits are set to all zeros (7'b0 = 0000_000) at power up in order to load
the factory configuration. However, in local update mode the control
register page address bits power up as (7'b1 = 0000_001) in order to
select the application configuration. Additionally, the control register
cannot be updated in local update mode, whereas a factory configuration
in remote update mode has write access to this register.
The control register bit positions are shown in Figure 8–7 and defined in
Table 8–4. In the figure, the numbers show the bit position of a setting
within a register. For example, bit number 8 is the enable bit for the
watchdog timer.
Figure 8–7. Remote System Upgrade Control Register
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Wd_timer[11..0]
Wd_en PGM[6..3] PGM[2..0] AnF
8–16
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008