EP2S130F1020I4 Datasheet, PDF (576/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Fast Passive Parallel Configuration
Figure 7–7 shows the timing waveform for FPP configuration when using
a MAX II device as an external host. This waveform shows the timing
when the decompression and/or the design security feature are enabled.
Figure 7–7. FPP Configuration Timing Waveform With Decompression or Design Security Feature
Enabled Notes (1), (2)
nCONFIG
t_CF2ST1
t_CFG
t_CF2CK
(3) nSTATUS
(4) CONF_DONE
t_STATUS
t_CF2ST0
t_{CF2CD tST2CK}
t_CL
t_CH
DCLK
DATA[7..0]
User I/O
12 341 234
(6)
1
t_CLK
Byte 0
Byte 1
(6)
Byte 2
t_DSU
t_DH
t_DH
High-Z
INIT_DONE
4
Byte n
(5)
(5)
User Mode
User Mode
t_CD2UM
Notes to Figure 7–7:
(1) This timing waveform should be used when the decompression and/or design security feature are used.
(2) The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
(3) Upon power-up, the Stratix II or Stratix II GX device holds nSTATUS low for the time of the POR delay.
(4) Upon power-up, before and during configuration, CONF_DONE is low.
(5) DCLK should not be left floating after configuration. It should be driven high or low, whichever is more convenient.
(6) DATA[7..0] are available as user I/O pins after configuration and the state of these pins depends on the
dual-purpose pin settings.
(7) If needed, DCLK can be paused by holding it low. When DCLK restarts, the external host must provide data on the
DATA[7..0] pins prior to sending the first DCLK rising edge.
7–24
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008