EP2S130F1020I4 Datasheet, PDF (647/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Configuring Stratix II and Stratix II GX Devices
Table 7–22. Dedicated Configuration Pins on the Stratix II and Stratix II GX Device (Part 2 of 10)
Pin Name
PORSEL
User Mode
Configuration
Scheme
N/A
All
Pin Type
Input
Description
Dedicated input which selects between a POR
time of 12 ms or 100 ms. A logic high (1.5 V,
1.8 V, 2.5 V, 3.3 V) selects a POR time of about
12 ms and a logic low selects POR time of
about 100 ms.
The PORSEL input buffer is powered by
V_{C C I N T} and has an internal 5-kpull-down
resistor that is always active. The PORSEL pin
should be tied directly to V_{C C P D} or GND.
nIO_PULLUP
N/A
All
Input
Dedicated input that chooses whether the
internal pull-up resistors on the user I/O pins
and dual-purpose I/O pins (nCSO, nASDO,
DATA[7..0], nWS, nRS, RDYnBSY, nCS,
CS, RUnLU, PGM[], CLKUSR, INIT_DONE,
DEV_OE, DEV_CLR) are on or off before and
during configuration. A logic high (1.5 V, 1.8 V,
2.5 V, 3.3 V) turns off the weak internal pull-up
resistors, while a logic low turns them on.
The nIO-PULLUP input buffer is powered by
V_{C C P D} and has an internal 5-kpull-down
resistor that is always active. The
nIO-PULLUP can be tied directly to V_{C CP D} or
use a 1-kpull-up resistor or tied directly to
GND.
MSEL[3..0]
N/A
All
Input
4-bit configuration input that sets the Stratix II
and Stratix II GX device configuration
scheme. Refer to Table 7–1 for the appropriate
connections.
These pins must be hard-wired to V_{C C P D} or
GND.
The MSEL[3..0] pins have internal 5-k
pull-down resistors that are always active.
Altera Corporation
January 2008
7–95
Stratix II Device Handbook, Volume 2