EP2S130F1020I4 Datasheet, PDF (628/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Passive Parallel Asynchronous Configuration
To simplify configuration and save an I/O port, the microprocessor can
wait for the total time of t_BUSY (max) + t_RDY2WS + t_W2SB before sending the
next data byte. In this set-up, nRS should be tied high and RDYnBSY does
not need to be connected to the microprocessor. The t_BUSY, t_RDY2WS, and
t_W2SB timing specifications are listed in Table 7–18 on page 7–82.
Next, the microprocessor checks nSTATUS and CONF_DONE. If nSTATUS
is not low and CONF_DONE is not high, the microprocessor sends the next
data byte. However, if nSTATUS is not low and all the configuration data
has been received, the device is ready for initialization. The CONF_DONE
pin will go high one byte early in parallel configuration (FPP and PPA)
modes. The last byte is required for serial configuration (AS and PS)
modes. A low-to-high transition on CONF_DONE indicates configuration
is complete and initialization of the device can begin. The open-drain
CONF_DONE pin is pulled high by an external 10-kpull-up resistor. The
CONF_DONE pin must have an external 10-k pull-up resistor in order for
the device to initialize.
In Stratix II and Stratix II GX devices, the initialization clock source is
either the internal oscillator (typically 10 MHz) or the optional CLKUSR
pin. By default, the internal oscillator is the clock source for initialization.
If the internal oscillator is used, the Stratix II or Stratix II GX device
provides itself with enough clock cycles for proper initialization.
Therefore, if the internal oscillator is the initialization clock source,
sending the entire configuration file to the device is sufficient to configure
and initialize the device.
You also have the flexibility to synchronize initialization of multiple
devices or to delay initialization with the CLKUSR option. The Enable
user-supplied start-up clock (CLKUSR) option can be turned on in the
Quartus II software from the General tab of the Device & Pin Options
dialog box. Supplying a clock on CLKUSR does not affect the
configuration process. After CONF_DONE goes high, CLKUSR is enabled
after the time specified as t_CD2CU. After this time period elapses, the
Stratix II and Stratix II GX devices require 299 clock cycles to initialize
properly and enter user mode. Stratix II devices support a CLKUSR f_MAX
of 100 MHz.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
This Enable INIT_DONE Output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used it is high because of an external 10-k
pull-up resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin goes low. When initialization is complete, the
7–76
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008