EP2S130F1020I4 Datasheet, PDF (619/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Configuring Stratix II and Stratix II GX Devices
f
For more information on configuring multiple Altera devices in the same
configuration chain, refer to the Configuring Mixed Altera FPGA Chains
chapter in the Configuration Handbook.
Figure 7–26 shows the timing waveform for the PS configuration scheme
using a configuration device.
Figure 7–26. Stratix II and Stratix II GX PS Configuration Using a Configuration Device Timing Waveform
nINIT_CONF or VCC/nCONFIG
t_POR
OE/nSTATUS
nCS/CONF_DONE
DCLK
DATA
t_OEZX
User I/O
INIT_DONE
t_DSU t_CL
D₀ D₁
t_CO
Tri-State
t_CH
t_DH
D₂ D₃
D_n
Tri-State
User Mode
(1)
Note to Figure 7–26:
(1) The initialization clock can come from the Stratix II or Stratix II GX device’s internal oscillator or the CLKUSR pin.
f
f
For timing information, refer to the Enhanced Configuration Devices
(EPC4, EPC8 & EPC16) Data Sheet chapter in volume 2 of the
Configuration Handbook or the Configuration Devices for SRAM-Based LUT
Devices Data Sheet chapter in volume 2 of the Configuration Handbook.
Device configuration options and how to create configuration files are
discussed further in the Software Settings chapter in volume 2 of the
Configuration Handbook.
PS Configuration Using a Download Cable
In this section, the generic term “download cable” includes the Altera
USB-Blaster^™ universal serial bus (USB) port download cable,
MasterBlaster^™ serial/USB communications cable, ByteBlaster^™ II
parallel port download cable, and the ByteBlaster MV parallel port
download cable.
In PS configuration with a download cable, an intelligent host (such as a
PC) transfers data from a storage device to the device via the USB Blaster,
MasterBlaster, ByteBlaster II, or ByteBlasterMV cable.
Altera Corporation
January 2008
7–67
Stratix II Device Handbook, Volume 2