EP2S130F1020I4 Datasheet, PDF (327/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

PLLs in Stratix II and Stratix II GX Devices
Table 1–17. Clock Resource Availability in Stratix II and Stratix II GX Devices (Part 2 of 2)
Description
Stratix II Device Availability
Stratix II GX Device Availability
Power-down mode
Global clock networks, regional clock GCLK, RCLK networks, dual-regional
networks, dual-regional clock region clock region
Clocking regions for high fan-out Quadrant region, dual-regional,
applications
entire device via global clock or
regional clock networks
Quadrant region, dual-regional,
entire device via GCLK or RCLK
networks
Global Clock Network
Global clocks drive throughout the entire device, feeding all device
quadrants. All resources within the device IOEs, adaptive logic modules
(ALMs), digital signal processing (DSP) blocks, and all memory blocks
can use the global clock networks as clock sources. These resources can
also be used for control signals, such as clock enables and synchronous or
asynchronous clears fed by an external pin. Internal logic can also drive
the global clock networks for internally generated global clocks and
asynchronous clears, clock enables, or other control signals with large
fanout. Figure 1–39 shows the 16 dedicated CLK pins driving global clock
networks.
Figure 1–39. Global Clocking Note (1)
CLK12-15
11 5
7
10
GCLK12 -15
16
16
CLK0-3
1
2
GCLK0-3
16
GCLK8-11 _{4 CLK8-11}
3
16
GCLK4-7
8
9
12 6
CLK4-7
Note to Figure 1–39:
(1) Stratix II GX devices do not have PLLs 3, 4, 9, and 10 or clock pins 8, 9, 10, and 11.
Altera Corporation
July 2009
1–63
Stratix II Device Handbook, Volume 2