EP2S130F1020I4 Datasheet, PDF (304/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Advanced Features
Manual Clock Switchover
Stratix II and Stratix II GX enhanced and fast PLLs support manual
switchover, where the clkswitch signal controls whether inclk0 or
inclk1 is the input clock to the PLL. If clkswitch is low, then inclk0
is selected; if clkswitch is high, then inclk1 is selected. Figure 1–23
shows the block diagram of the manual switchover circuit in fast PLLs.
The block diagram of the manual switchover circuit in enhanced PLLs is
shown in Figure 1–23.
Figure 1–23. Manual Clock Switchover Circuitry in Fast PLLs
clkswitch
inclk0
inclk1
muxout
n Counter
refclk
PFD
fbclk
Figure 1–24 shows an example of a waveform illustrating the switchover
feature when controlled by clkswitch. In this case, both clock sources
are functional and inclk0 is selected as the primary clock. clkswitch
goes high, which starts the switch-over sequence. On the falling edge of
inclk0, the counter’s reference clock, muxout, is gated off to prevent
any clock glitching. On the rising edge of inclk1, the reference clock
multiplex switches from inclk0 to inclk1 as the PLL reference. When
the clkswitch signal goes low, the process repeats, causing the circuit to
switch back from inclk1 to inclk0.
1–40
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009